Apparatus and method for a low-rate data transmission mode over a power line

ABSTRACT

In one embodiment, a system and method for receiving information over a power line in accordance with the HomePlug specification is described. The receiver side of the method involves separation of the data within a payload of an incoming frame into a plurality of blocks. Thereafter, both frame control symbols and data within the blocks are processed by Frame Control Forward Error Correction (FEC) decoding logic.

FIELD

[0001] The invention relates to the field of communications. Inparticular, one embodiment of the invention relates to an apparatus andmethod providing for low-rate data transmissions over a power line.GENERAL BACKGROUND

[0002] Originally, power line networking was conceived for thenetworking and high-speed transport of data in small office and homeoffice environments. Recently, a specification entitled “HomePlug 1.0Specification,” was published by the HomePlug Network Alliance. TheHomePlug 1.0 Specification provides functions, operations and interfacecharacteristics for high-speed networking based on Orthogonal FrequencyDivision Multiplexing (OFDM) modulation and using power line wiring asits medium.

[0003] The HomePlug 1.0 Specification identifies four modes ofoperation, all supporting high-rate data transmissions over a powerline. These modes of operation include a Robust (ROBO) mode, aDifferential Binary Phase Shift Keying (DBPSK) mode and two differentspeeds of Differential Quadrature Phase Shift Keying (“¼” DQPSK and “¾”DQPSK). For instance, the ROBO mode is a robust form of DifferentialBinary Phase Shift Keying (DBPSK) that provides extensive time andfrequency diversity to improve performance of a system under adverseconditions.

[0004] The maximum possible PHY layer payload transmission ratesupported by these modes of operation normally ranges from one megabitsper second (Mbps) for ROBO mode to 13 megabits per second (Mbps) forDQPSK (¾). These rates are realized by employing an extensive digitalsignal processor (DSP) computational power at the transmitter andreceiver. It is now being realized that the current HomePlug standardfails to provide a low-cost solution to support stations operating atsubstantially lower data rates such as automation control devices (e.g.,home appliances, security and monitoring devices and light/temperaturescheduling devices).

[0005] The development of a mode of operation that supports low-ratedata transmissions without altering operations supported by the currentHomePlug standard may be useful for a variety of applications. Also,such development would provide substantial cost savings to allowmanufacturers to produce different cost and complexity levels ofHomePlug compliant stations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The features and advantages of the invention will become apparentfrom the following detailed description of the invention in which:

[0007]FIG. 1 is an exemplary embodiment of a communication systemoperating in accordance to the HomePlug standard.

[0008]FIG. 2 is a general, exemplary embodiment of a HomePlug compliantstation.

[0009]FIG. 3 is an exemplary embodiment illustrative of generaloperations of logic within a MAC layer of a HomePlug compliant stationfor tracking channel estimation information.

[0010]FIG. 4 is an exemplary embodiment of general Transmit (TX)operations conducted by the PHY layer of a first HomePlug compliantstation of FIG. 1.

[0011]FIG. 5 is an exemplary embodiment of general Transmit (TX)operations conducted by the PHY layer of a HomePlug compliant station ofFIG. 1 during LORA mode.

[0012]FIG. 6 is an exemplary embodiment of general Receive (RX)operations conducted by a PHY layer of a receiving HomePlug compliantstation of FIG. 1 upon detecting transmissions in LORA mode.

[0013]FIG. 7 is an exemplary embodiment of general TX operationsconducted by a PHY logic of a low-rate, HomePlug compliant station ofFIG. 1.

[0014]FIG. 8 is an exemplary flowchart of the TX and RX operations forsupporting low-rate data transmissions.

DETAILED DESCRIPTION

[0015] Herein, one embodiment of the invention relates to an apparatusand method for enabling low-rate transmission of information over apower line operating in accordance with the HomePlug standard. This maybe accomplished through the creation of a new mode of operation referredto as “low-rate automation control” or (LORA) mode.

[0016] HomePlug compliant stations configured to support the LORA modeoffer a cost-effective solution. For instance, low-rate HomePlugcompliant stations (e.g., network appliances, networked thermostats orlighting controls, etc.) may be configured with logic that exclusivelysupports a LORA mode of operation. Such logic, namely its controller,analog front-end (AFE), filters and the like would be less complex andthus less costly to produce. Also, if implemented as hardware, suchlogic would occupy less silicon area.

[0017] In the following description, certain terminology is used todescribe features of the invention. For instance, a “frame” is generallydefined to a particular grouping of data for transport over a powerline. Such data may include symbols that enable the transmission of bitsof information, namely address, data, control or any combinationthereof.

[0018] A “power line” is generally defined as one or more physical orvirtual links, namely information-carrying mediums to establish acommunication pathway. For this embodiment, a power line may beAlternating Current (AC) electrical wiring. Of course, as anotherembodiment, a power line may be a telephone line (e.g., twisted pair) oranother electrical wire type, optical fiber, cable, bus trace, or even awireless path (e.g., air in combination with wireless signalingtechnology).

[0019] A “HomePlug compliant station” is an electronic device or adapterthat is configured to receive data over a power line and transfer datain accordance with current or future HomePlug standards (genericallyreferred to herein as the “HomePlug standard”). The current version ofthe HomePlug standard is entitled “HomePlug 1.0 Specification,”published by the HomePlug Network Alliance on or around Jun. 30, 2001.Examples of certain types of stations include a computer (e.g., agateway or server, hand-held “PDA”, a data terminal, laptop, desktop,etc.), a modem, a set-top box, an automation control device (e.g.,network appliance, networked security equipment, networked thermostat,lighting scheduling equipment, etc.), or even a communication device(e.g., telephone, cellular phone, pager, etc.).

[0020] of course, as an adapter, a HomePlug compliant station isconfigured for either a two or three prong power cord for coupling to awall socket or perhaps a RJ-11 telephone cord for coupling to an RJ-11jack. The adapter converts information formatted in accordance with theHomePlug standard into another format readable by another station, whichis coupled to the adapter via a connector (e.g., RJ-11 jack, serialport, Universal Serial Bus “USB” port, parallel port or any combinationthereof) or through wireless communications. To support a wirelesscommunication scheme, the adapter would employ a wireless transceiver orreceiver operating in accordance with a wireless communication protocol(e.g., Bluetooth, HyperLAN/2, IEEE 802.11, etc.).

[0021] A HomePlug compliant station comprises “logic,” namely hardware,firmware, software or any combination thereof that performs a desiredfunction on input information. For example, in one embodiment, the logicmay be adapted as circuitry that performs various operations on aplurality of data blocks. This circuitry may include a “controller” suchas a digital signal processor, a general microprocessor, amicro-controller, an application specific integrated circuit (ASIC), afield programmable gate array, a state machine, combinatorial logic orthe like.

[0022] When implemented as software, the invention is characterized, atleast in part, as a series of instructions that, when executed, performa certain function. The software may be stored in a machine-readablemedium, including but not limited to an electronic circuit, asemiconductor memory device, a read only memory (ROM), a flash memory,an erasable ROM (EROM), a floppy diskette, a compact disk, an opticaldisk, a hard disk, a fiber optic medium, a radio frequency (RF) link orthe like. Such software may be executed by the controller.

[0023] I. General System Architecture

[0024] Referring to FIG. 1, an exemplary embodiment of a communicationsystem operating in accordance to a HomePlug standard is shown.Communication system 100 includes a plurality of stations 110 ₁-110 _(X)(X≧1) in communication with each other via a power line 120 routedthrough an establishment (e.g., residence, apartment building, place ofbusiness, etc.). With respect to one embodiment, power line 120 may bean AC power line normally carrying an AC voltage (e.g., 120 VAC to 240VAC) over which data is transmitted in accordance with the HomePlugstandard. For another embodiment, power line 120 may be a telephone line(e.g., twisted pair) over which data is transmitted in accordance withthe HomePlug standard.

[0025] Stations 110 ₁-110 _(X) are coupled to power line 120 viadedicated links 130 ₁₋₁₃₀ _(X), which may support wired or wirelesscommunications. These stations 110 ₁-110 _(X) exchange information overpower line 120 using a plurality of carriers. In general, a “carrier” isan electromagnetic pulse or wave transmitted at a steady base frequencyof alternation on which information can be imposed. Of course, whenpower line 120 is fiber optic medium, the carrier may be a light beam onwhich information can be imposed.

[0026] As shown, different types of stations 110 ₁-110 _(X) may beemployed in communication system 100. For example, station 110 ₁ is aHomePlug compliant station supporting both high-rate and low-rate datatransmissions. Hence, HomePlug compliant station 110 ₁ may operate in aplurality of operating modes, namely Robust (ROBO) mode, BPSK mode, twodifferent QPSK modes and Low-Rate Automation control (LORA) modedescribed below. Station 110 ₂ is a “low-rate” HomePlug compliantstation that exclusively operates in the LORA mode. Station 1103 is anadapter while station 110 ₄ is a wireless adapter.

[0027] As an optional feature, a network transceiver 140 may be furthercoupled to power line 120 and provide communications to a network 150separate and apart from the network formed by power line 120. Thenetwork 150 may be employed as a local area network, a wide area network(WAN) such as the Internet or another type of network architecture. The“network transceiver” may include a computer (e.g., gateway, server,etc.), a router, or a switching device for example.

[0028] II. Embodiments of HomePlug Compliant Stations

[0029] A. General Architecture

[0030] Referring to FIG. 2, an exemplary embodiment of a HomePlugcompliant station 110 _(X) is shown. In general, HomePlug compliantstation 110 _(X) includes a physical layer (PHY) layer 200 and a mediaaccess control (MAC) layer 210. PHY layer 200 comprises logic that isresponsible for at least controlling forward error correction,modulation/demodulation and maintaining electrical connections over awire-side interface 220 associated with power line 120 as needed. MAClayer 210 comprises logic that at least controls segmentation andreassembly of HomePlug frames between PHY layer 200 and a logicalinterface 230.

[0031] B. General Use of Tone Map Index in the MAC Layer of a HomePlugCompliant Station

[0032] Referring to FIG. 3, an exemplary embodiment of a generaloperations of logic within a MAC layer of any type of HomePlug compliantstation is shown. For this embodiment, as an example, the HomePlugcompliant station stores a plurality of tone map indices 250. Normally,a “tone map index” is a multi-bit vector that indicates what carriersare reliable for communication with a particular station. For thisillustrative embodiment, a tone map index may be a 84-bit vector thatindicate which carriers are unreliable.

[0033] Herein, one of the tone map indices, namely tone map index 260,is reserved exclusively to identify a HomePlug compliant station isoperating and transmitting information in accordance with the LORA modeof operation. The control bits associated with tone map index 260 areloaded with other control information into logic at the PHY layer forplacement into frame control symbols of an intermediary frame.

[0034] Thus, upon detecting transmissions in the LORA mode, thereceiving HomePlug compliant station, if able, operates in LORA mode forthat communication session. Otherwise, the transmissions are treated ashigh-speed data transfers using both Data FEC and Frame Control FECdecoding logic as described in FIG. 6.

[0035] In the MAC layer, during LORA mode, a bit transfer rate ofapproximately 625 kilobits per second (Kbps) is achieved. This iscomputed by the maximum number (40) of FEC blocks (described below)multiplied by 25 bits carried per FEC block divided by 1.6 milliseconds(i.e. transmission duration for one frame). This differs from ROBO modethat supports 870 Kbps.

[0036] C. General TX/RX Operations of a PHY Layer of a First Embodimentof a HomePlug Compliant Station

[0037] Referring now to FIG. 4, a first exemplary embodiment of generalTransmit (TX) operations conducted by logic at the PHY layer of aHomePlug compliant station 110 _(X) is shown. The PHY layer logicreceives information from MAC layer 210 and produces a HomePlug frame300. HomePlug frame 300 features a first delimiter 310, a seconddelimiter 320 and a payload 330.

[0038] As shown, first delimiter 310 is used to identify the start ofHomePlug frame 300. For this embodiment, first delimiter 310 includes afirst frame control field 311 containing a plurality of frame controlsymbols, such as four (4) OFDM frame control symbols 312-315 forexample. Also, first delimiter 310 includes a field 316 for a preamblesignal that is placed therein after encoding has been completed.

[0039] As further shown, second delimiter 320 includes a second framecontrol field 321, which again features frame control symbols, namelyfour (4) OFDM frame control symbols 322-325 for this embodiment. TheOFDM frame control symbols 322-325 are used to identify the end ofHomePlug frame 300 and may be identical to OFDM symbols placed in firstdelimiter 310. Second delimiter 320 includes a field 326 for thepreamble signal to be placed therein after encoding has been completed.

[0040] An embodiment of a frame control field 311 or 321 for delimiters310 or 320 is shown in Table 1. For example, frame control field 311enables the transfer of twenty-five (25) bits of control information 327divided up into a plurality of subfields such as a delimiter type (DT)subfield, variant (VF) subfield and frame control check sequence (FCCS)subfield for example. In one embodiment, one bit of frame control field311 may be used to signal a receiving HomePlug compliant station toextract certain data bits from the payload for routing over a separatecommunication channel for enhanced control functionality as describedbelow. TABLE 1 Bit Number Bits Field (Symbol No.) (Symbol) Definition CC24 (1)  1 (1) Contention Control DT 23-21 (2)  3 (2) Delimiter Type VF20-8 (3) 13 (3) Variant Field FCCS  7-0 (4)  8 (4) Frame Control CheckSequence

[0041] The DT subfield may be adapted as a 3-bit field that identifiesthe delimiter and its position relative to the resultant HomePlug frame.The FCCS subfield features a cyclic redundancy check (CRC). For thisembodiment, the CRC is 8-bits in length.

[0042] Moreover, the VF subfield may be adapted to include a framelength subfield and a tone map index (TMI) subfield. The frame lengthsubfield may be used to indicate the length of the HomePlug frame interms of the number of 40-symbol Physical (PHY) transmission blocks,followed by zero or one 20-symbol PHY transmission blocks. This allowsframe length subfield to cover overall symbol numbers ranging from 20symbols to 160 symbols for this embodiment. In the ROBO and LORA modes,the number of symbols should be a multiple of 40. The TMI subfieldcontains an index to the receiving HomePlug compliant station's tone maptable for use in encoding and decoding and perhaps LORA mode detectionas described below.

[0043] Referring still to FIG. 4, during ROBO mode or another high-speeddata transmission mode of operation, control information 327 (e.g., bitsassociated with the CC, DT, VF and FCCS subfields) is processed by aFrame Control Forward Error Correction (FEC) encoding logic 340 toproduce frame control symbols 312-315 and 322-325.

[0044] For this embodiment, Frame Control FEC encoding logic 340includes an encoder 341 and/or a frame control interleaver 342. Encoder341 may be adapted to encode twenty-five (25) control bits into a100-bit code word. Frame control interleaver 342 redundantly maps the100-bits into four (4) symbols of up to 84-bits each. Such operationsare described on pages 9-12 of the HomePlug 1.0 Specificationincorporated herewith by reference.

[0045] In addition, during ROBO mode, incoming data 331 to betransmitted from the HomePlug compliant station 110 _(X) is processed bydifferent logic referred to as a “Data FEC encoding logic” 350. Data FECencoding logic 350 is adapted to perform scrambling, Reed-Solomonencoding, convolutional encoding and complex bit interleaving operationson data 331, and thereafter, to load the encoded and/or interleaved datawithin payload 330. Such operations are described on pages 13-18 of theHomePlug 1.0 Specification incorporated herewith by reference.

[0046] An intermediary frame 360, produced by the combined outputs ofboth FEC encoding logic units 340 and 350, is processed by a modulationunit 370 (e.g., an OFDM modulator) to produce the HomePlug frame 300.The HomePlug frame 300 is converted to an analog format by an analogfront-end (AFE) 380 before transmission over different channelssupported by the power line.

[0047] During LORA mode, however, both data 331 and control information327 are processed by Frame Control FEC encoding logic 340, therebyavoiding usage of scrambler, Reed-Solomon encoder, convolutional encoderand complex bit interleaving.

[0048] As shown in FIG. 5, control information 327 (e.g., bitsassociated with the CC, DT, VF and FCCS subfields) is processed by FrameControl FEC encoding logic 340 to produce frame control symbols 312-315and 322-325 for a HomePlug frame 400. During such processing, theHomePlug compliant station can detect whether such transmissions are inaccordance with the LORA mode of operation through analysis of thecontrol information 327 to be transmitted for example.

[0049] For this embodiment, Frame Control FEC encoding logic 340 isadapted to detect when HomePlug frame 400 is being transmitted while theHomePlug compliant station is in LORA mode. This may be accomplished byFrame Control FEC encoding logic 340 analyzing control informationassociated with the TMI subfield, which is carried by frame controlsymbol 314. In the event that the control information associated withthe TMI subfield indicates a specific tone map index used to identify atransmission in LORA mode, all encoding for that communication sessionis handled by Frame Control FEC encoding logic 340.

[0050] In addition, Frame Control FEC encoding logic 340 is furtherconfigured to determine the length (in symbols) of payload 330 forHomePlug frame 400. In particular, Frame Control FEC encoding logic 340is adapted to analyze the control information associated with a lengthsubfield of the VF subfield, which is also carried by frame controlsymbol 314.

[0051] Frame Control FEC encoding logic 340 further receives datadestined for payload 330 of HomePlug frame 400. During the LORA mode,multiple FEC blocks 410 are generated by Frame Control FEC encodinglogic 340, each FEC block 410 _(X) carrying a plurality of input bits.For instance, a first grouping of input bits 420 (e.g., twenty-five “25”input bits) is encoded and/or interleaved for symbol transmissionredundancy to produce multiple symbols forming a first FEC block 410 ₁.A second grouping of input bits 421 is encoded and/or interleaved toproduce multiple symbols forming a second FEC block 410 ₂. This processis repeated until all of the FEC blocks 410 are processed.

[0052] The input bits associated with each grouping are provided throughone or more communication paths. For example, of the 25 input bitsassociated with first grouping 420, 3 bytes of data 430 are providedover a first path. A final data bit 431, representing the mostsignificant or the least significant bit as shown, is provided throughanother path, namely a separate communication link carrying informationindependently from the first path. This data bit 431 may be extracted bythe receiving HomePlug compliant station during a communication sessionand used for additional control functionality as described below.

[0053] For example, final data bit 431 can be used as a parity bit tocheck for validity of data bits 430. Alternatively, final data bit 431may be used to provide additional information pertaining to thetransmitting HomePlug compliant station or any logic implementedtherein. This may be accomplished by the Frame Control FEC decodinglogic at the receiving HomePlug compliant station extracting final databit 431 and routing that data bit over a separate communication channel(referred to as a “slow communication channel”). The “slow communicationchannel” is a virtual parallel path to the communication pathway alreadyestablished for the transmission of data bits 430.

[0054] For instance, information may involve operational status of atransmitting HomePlug compliant station or logic employed therein (e.g.,powered on/off, motor speed, measured temperature, etc.). Theinformation may involve sensed state changes of the station. Theinformation may involve any other information deemed relevant to controloperations of the transmitting HomePlug compliant station.

[0055] It is contemplated that a higher level protocol at thetransmitting HomePlug compliant station is used to signal the receivingHomePlug compliant station that slow communication channel isoperational. This signaling technique can be accomplished throughflag(s) (e.g., flag set within MAC layer software), by setting aselected data bit within one or more successive frame control fields ofa delimiter, or by any other technique. If the slow communicationchannel is not operational, the final data bits associated with all FECblocks are repeatedly placed in a selected state (e.g., active “1” orinactive “0”).

[0056] The information carried by the slow communication channel is 40bits in a frame with 160 OFDM symbols. The rate for such channel wouldbe 40 divided by 1.6 milliseconds, namely 25 Kbps. This allows the slowcommunication channel to be used for control applications where very lowbit rates are required and it can coexist with the main LORA channelover the power line.

[0057] After processing multiple FEC blocks, “M” FEC blocks 410 ₁-410_(M) are combined by logic within the PHY layer, normally separate fromFrame Control FEC encoding logic 340, to form a PHY transmission block440 ₁. For this embodiment, ten (10) FEC blocks 410 ₁-410 ₁₀ arecombined to form a PHY transmission block 440 ₁. Normally, the size ofpayload 330 is “N” PHY transmission blocks 440 ₁-440 _(n), where “N”ranges from one to four. In the event that a second PHY transmissionblock 440 ₂ is contained in payload 330, it is produced by combining thenext series of “M” FEC blocks. This process continues until N×M FECblocks have been encoded and/or interleaved by Frame Control FECencoding logic 340 and combined as PHY transmission blocks in formingpayload 330 of an intermediary frame 450.

[0058] The intermediary frame 450 is modulated by a modulation unit 460to produce HomePlug frame 400 that is transmitted by an analog front end(not shown) over a power line. As shown, Data FEC encoding logic 350 isnot used for any encoding operations during LORA mode.

[0059] Referring now to FIG. 6, general Receive (RX) operationsconducted by PHY layer 500 of a receiving HomePlug compliant station 110_(X) of FIG. 2 is shown. Logic of PHY layer 500 receives HomePlug frame400 over a power line 120. This logic includes an analog front-end (AFE)510 to place frame 400 into a different form and a demodulator 515 todemodulate the received HomePlug frame 400 in accordance with any typeof demodulation scheme such as OFDM demodulation. Thereafter,information associated with demodulated HomePlug frame is routed toFrame Control FEC decoding logic 530 and the information associated withdemodulated HomePlug frame is routed to Data FEC decoding logic 520. Incase of detection of LORA mode, however, both a payload data 330 andframe control symbols 312-315 and 322-325 of the received frame arerouted to the Frame Control FEC decoding logic 530.

[0060] For instance, for this embodiment, at least one of frame controlsymbols (e.g., symbol 314) is de-interleaved and/or decoded to determinewhether the incoming HomePlug frame is transmitted by a stationoperating in LORA mode. Such determination may be accomplished bydetecting a specific tone map index carried by frame control symbol 314.Such analysis may be handled by dedicated logic (not shown) or by FrameControl FEC decoding logic 530.

[0061] Upon detection that the transmitting HomePlug compliant stationis operating in LORA mode, the PHY logic 500 within the receivingHomePlug compliant station de-interleaves and decodes frame controlsymbols 312-315 as normal and segments data within payload 330 into “N”PHY transmission blocks 540 ₁-540 _(N) (N≧1). Each PHY transmissionblock 540 ₁, . . . , 540 _(N) is 40-symbols in length for thisembodiment. Subsequent or concurrent to the segmentation operation, thedata associated with these PHY transmission blocks 540 ₁-540 _(N) isprocessed by Frame Control FEC decoding logic 530.

[0062] More specifically, with respect to a first PHY transmission block540 ₁, it is separated into “M” FEC blocks 550 ₁-550 _(M). For thisembodiment, each FEC block 550 ₁-550 _(M) represents four symbols formedby a corresponding encoding/interleaving operation(s). Each of these FECblocks 550 ₁-550 _(M) is separately de-interleaved (if interleavingperformed at the transmitting station) and then decoded to recover theinput bits. Such de-interleaving and/or decoding occurs for each FECblock 550 ₁, . . . , 550 _(M) until all of the FEC blocks for first PHYtransmission block 540 ₁ and subsequent PHY transmission block(s) 540 ₂,. . . , 540 _(N) have been processed.

[0063] In the event receiving HomePlug compliant station 110 _(X)detects slow communication channel data (e.g., specific bit recoveredfrom frame control symbols 312-315 is set), one of the bits recoveredfrom each FEC block is separately used for control purposes as brieflydescribed above.

[0064] In the PHY layer, during LORA mode, a bit transfer rate ofapproximately 7600 Kbps is achieved. This is computed by the maximumnumber of reliable carriers (76) multiplied by the number of symbolswithin the PHY transmission blocks (160) divided by 1.6 milliseconds(i.e. transmission duration for one frame). This transmission rate isequivalent to stations operating in ROBO mode.

[0065] D. General TX/RX Operations of a PHY Layer of a Second Embodimentof a HomePlug Compliant Station

[0066] Referring now to FIG. 7, an exemplary embodiment of general TXoperations conducted by PHY logic 600 of a low-rate, HomePlug compliantstation 110 ₂ of FIG. 1 is shown. Logic within a PHY layer 600 oflow-rate, HomePlug compliant station 110 ₂ comprises Frame Control FECencoding logic 340 and excludes Data FEC encoding logic. This reducescomplexity of the PHY logic and provides cost benefits duringmanufacture.

[0067] As shown, control information 327 (e.g., bits associated with theCC, DT, VF and FCCS subfields) is processed by Frame Control FECencoding logic 340 to produce frame control symbols 312-315 and 322-325used by a resultant HomePlug frame (not shown). During such processing,the HomePlug compliant station can detect whether such transmissions arein accordance with the LORA mode of operation by analysis of controlinformation 327.

[0068] Herein, Frame Control FEC encoding logic 340 detects thattransmissions are being conducted under the LORA mode by analyzingcontrol information 327. In the event that the control informationidentifies a transmission as being conducted in LORA mode, all encodingfor that communication session is handled by Frame Control FEC encodinglogic 340.

[0069] Frame Control FEC encoding logic 340 is further configured todetermine the length (in symbols) of payload 330 for generating theHomePlug frame. One way to accomplish this task is to analyze thecontrol information contained within a length subfield of the VFsubfield, which is carried by frame control symbol 314.

[0070] Frame Control FEC encoding logic 340 further receives datadestined for payload 330 of the HomePlug frame. During the LORA mode,multiple FEC blocks 410 are generated by Frame Control FEC encodinglogic 340, each FEC block 410 _(X) carrying a plurality of input bits.For instance, a first grouping of input bits 420 (e.g., twenty-five “25”input bits) is encoded and/or to produce multiple symbols forming firstFEC block 410 ₁. A second grouping of input bits 421 is encoded and/orinterleaved to produce multiple symbols forming second FEC block 410 ₂.This process is repeated until all of the FEC blocks are processed.

[0071] Within each grouping, input bits may be provided over multiplecommunication paths. For example, for the 25 input bits associated withfirst grouping 420, three (3) bytes of data 430 are providedindependently from final data bit 431. The presence of data bit 431 maybe used as an effective technique for providing additional status orother control functionality pertaining to the transmitting HomePlugcompliant station.

[0072] After processing multiple FEC blocks, “M” FEC blocks 410 ₁-410_(M) are combined to form a PHY transmission block 440 ₁. For thisembodiment, ten (10) FEC blocks 410 ₁-410 ₁₀ are combined to form PHYtransmission block 440 ₁. In the event that a second PHY transmissionblock 440 ₂ is contained in payload 330, it is produced by combining thenext “M” FEC blocks. This process continues until “N” PHY transmissionblocks have been filled to produce an intermediary frame 450.Intermediary frame 450 is then modulated to produce a HomePlug framethat is transmitted by an analog front-end over a power line as shown inFIG. 5.

[0073] E. General Flowchart for Supporting LORA Mode

[0074] Referring to FIG. 8, an exemplary flowchart of the operations forsupporting low-rate data transmissions in accordance with the LORA modeis shown. Initially, when operating in LORA mode, the HomePlug compliantstation configures a transmitted frame to identify that the transmissionis being conducted in the LORA mode (blocks 700 and 705). This may beaccomplished by setting control information to be carried by one or moreframe control symbols to a specific value.

[0075] The control information is encoded and/or interleaved by theFrame Control FEC encoding logic to produce the frame control symbols(block 710). Similarly, data destined for the payload is encoded and/orinterleaved by the Frame Control FEC encoding logic to produce FECblocks (block 715). Multiple FEC blocks are combined to produce one PHYtransmission block. One of more PHY transmission blocks form the payloadof the frame (block 720). If there are an insufficient number of FECblocks to provide a full PHY transmission pad, padding may be provided.For this embodiment, the frame control symbols and payload are modulatedto produce a HomePlug frame (block 725), which is normally converted toan analog form for routing over the power line (block 730).

[0076] At the receiving HomePlug compliant station, the analog signalsforming the HomePlug frame are recovered and placed the HomePlug frameinto a digital form (block 735). The recovered HomePlug frame isdemodulated and the transmission is analyzed to determine if thecommunication session under LORA mode is requested (blocks 740 and 745).This may involve the Frame Control FEC decoding logic to de-interleaveand/or decode one or more of the frame control symbols. If LORA mode isdetected for this communication session, the remainder of the framecontrol symbols (if not all de-interleaved and decided) and data withinthe payload are de-interleaved and/or decoded to recover the controlbits and the input data bits (block 750).

[0077] While certain exemplary embodiments have been described and shownin the accompanying drawings, it is to be understood that suchembodiments are merely illustrative of the invention in order to providea thorough understanding of the invention. Also, well-known circuits arenot set forth in detail in order to avoid unnecessarily obscuring theinvention.

What is claimed is:
 1. A method for receiving information over a powerline, comprising: separating data within a payload of an incoming frameinto a plurality of blocks; and processing both frame control symbolsand data within the blocks by Frame Control Forward Error Correction(FEC) decoding logic.
 2. The method of claim 1 further comprisingseparating data bits recovered from each block for transmission over atleast two different communication paths.
 3. The method of claim 1,wherein each of the plurality of blocks being equal in length.
 4. Themethod of claim 1, wherein the separating of the data comprises:separating the payload into at least two physical transmission blocks;and separating each of the at least two physical transmission blocksinto the plurality of blocks, each block having a length less thanone-half a length of the physical transmission block.
 5. The method ofclaim 4, where the length of each physical transmission block beingapproximately forty symbols.
 6. The method of claim 5, wherein thelength of each block being approximately four symbols.
 7. The method ofclaim 6, wherein the four symbols of each block carry a plurality ofinput bits.
 8. The method of claim 1, wherein the processing of both theframe control symbols and data of the payload includes de-interleavingand decoding operations.
 9. The method of claim 8, prior to conductingat least one of the de-interleaving and decoding operations on the data,the method further comprises: recovering at least one bit from one ofthe frame control symbols to detect whether the frame is beingtransmitted in accordance with a low-rate automation control (LORA)mode.
 10. A method comprising: determining whether a HomePlug compliantstation is operating in a low-rate automation control (LORA) mode;encoding both control information and data within a Frame ControlForward Error Correction (FEC) encoding logic if the HomePlug compliantstation is operating in the LORA mode.
 11. The method of claim 10further comprising: upon determining that the HomePlug compliant stationis not operating in the LORA mode, producing frame control symbols for aframe by the Frame Control FEC encoding logic, and producing datacorresponding to a payload of the frame by a Data FEC encoding logic.12. The method of claim 10, wherein the determination whether theHomePlug compliant station is operating in the LORA mode comprisesdetermining whether a predetermined tone map index is part of thecontrol information.
 13. The method of claim 10, wherein the data beingencoded is received over at least two communication paths, at least onebit from each of the plurality of blocks is received over a firstcommunication path while the remaining twenty-four input bits of each ofa plurality of blocks is received over a second communication path. 14.The method of claim 13 further comprising: placing the encoded datawithin a HomePlug frame; and transmitting the HomePlug frame over thepower line via a primary channel.
 15. The method of claim 14 furthercomprising: placing the extracted at least one bit into a frame fortransmission over the power line via a secondary channel.
 16. A HomePlugcompliant station comprising: a media access control (MAC) layer; and aphysical layer in communication with the MAC layer, the physical layerincluding a Frame Control Forward Error Correction (FEC) encoding logicto encode and interleave both data and control information associatedwith the frame during a first mode of operation.
 17. The HomePlugcompliant station of claim 16, wherein the physical layer furtherincludes a data FEC encoding logic that, during a second mode ofoperation, encodes and interleaves the data while the Frame Control FECencoding logic encodes and interleaves only the control information. 18.The HomePlug compliant station of claim 17, wherein the controlinformation includes a tone map index value.
 19. The HomePlug compliantstation of claim 16, wherein the Frame Control FEC encoding logic (i)determining a mode of operation of the HomePlug compliant station, and(ii) encoding the control information and data in an iterative manner.20. The HomePlug compliant station of claim 16, wherein the FrameControl FEC encoding logic (i) determining a mode of operation of thestation, (ii) encoding and interleaving the data to produce a pluralityof blocks and the control information to produce frame control symbols,(iii) combining multiple blocks, each being generally equivalent in sizeto four symbols to produce at least two physical transmission blocks,and (iv) combining the at least two physical transmission blocks, eachof the physical transmission blocks being generally equivalent in sizeto forty symbols, to produce a payload of an outgoing frame.
 21. AHomePlug compliant station comprising: a receiver to retrieve anincoming frame from a power line; and a Frame Control Forward ErrorCorrection (FEC) decoding logic to de-interleave and decode both dataand control information during a first mode of operation.
 22. TheHomePlug compliant station of claim 21 further comprising: a data FECencoding logic to de-interleave and decode only data associated with theincoming frame while the Frame Control FEC decoding logic de-interleavesand decodes only control information associated with the incoming framewhen the station is operating in a second mode of operation.
 23. TheHomePlug compliant station of claim 21, wherein the data is containedwithin the payload of the incoming frame.
 24. The HomePlug compliantstation of claim 23, wherein the Frame Control FEC encoding logic (i)determining a mode of operation associated with a transmittingstation,(ii) separating the data of the payload into a plurality ofphysical transmission blocks, each of the physical transmission blocksbeing generally equivalent in size to forty symbols, (iii) separatingeach of the physical transmission blocks into the plurality of blocks,each of the plurality of blocks being equivalent in size to foursymbols, and (iv) de-interleaving and decoding the symbols within eachof the plurality of blocks by the Frame Control FEC decoding logic torecover the data when the determined mode of operation is the first modeof operation.
 25. Software embodied in a machine-readable medium andexecuted by a processor, comprising: a first software module to separatedata within a payload of an incoming frame into a plurality of blocks;and a second software module to process both frame control symbols anddata within the blocks, the second software module operating as a FrameControl Forward Error Correction (FEC) decoding logic.